1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device and a method of production of the same, more particularly relates to a semiconductor nonvolatile memory device having a charge storing layer for storing a charge between a gate electrode of a transistor and a channel formation region and to a method of production of the same.
2. Description of the Related Art
At the present time, semiconductor nonvolatile memory devices are being actively developed. Research and development are being conducted in various structures and configurations primarily focusing on flash memories of a floating gate structure. Flash memories may be roughly classified into a NAND type and a NOR type array from the viewpoint of the cell configuration.
Among the above, the NAND type array connects a plurality of memory cells in series and has common selection transistors and bit lines. For example, when connecting eight memory cells, 1/2 of a contact for data input/output is shared by eight memory cells and therefore there is 1/16 of a contact per cell. Similarly, selection gates and a source line are all shared by the eight cells. Accordingly, as described above, the surface area per cell becomes close to the area occupied by a memory transistor and therefore the area of the memory cell is very small. Random access is not possible because of the structure, but it is advantageous in the points of the increased degree of integration, the increased capacity, and accordingly the lowered costs. For AV (audio and video) use or for data storage use or other applications, low priced, large capacity flash memories are sought. They are suited for example for replacing magnetic recording means such as HDD's (hard disk drives).
On the other hand, in the NOR type array, due to its structure, there is 1/2 of a contact per cell. This is disadvantageous in the point of the degree of integration in comparison with the NAND type array, but has the advantage that high speed random access reading is possible. For high speed reading applications, this may be expected to become part of the main memories in the future. The above NAND type or NOR type memory transistors may be of the floating gate type or an SIOS (or MONOS) type.
A table comparing the various performances of the NAND type and the NOR type array is shown next.
TABLE 1 ______________________________________ Read Random Write Erase Degree of speed access method method integration ______________________________________ NAND Slow Poor FN FN Good type NOR Fast Good CHE FN Fair type ______________________________________ FN: Fowler Nordheim type tunnel injection CHE: Channel hot electron type tunnel injection
Here, a circuit diagram of a NOR type memory cell is shown in FIG. 15. In the erasing of data, a low voltage Vcg is supplied to a control gate CG, a high voltage Vs is supplied to a source S, and a bit line B and a substrate Sub are made open. By this, due to the Fowler Nordheim type tunneling phenomenon, electrons in the floating gate are drained and the data is erased. As this erasure, batch erasing for every erasing sector is possible.
On the other hand, in a NAND type memory cell, as shown in FIG. 16, for example eight memory transistors are connected in series to constitute a NAND column. Selection transistors for selecting the present NAND column are formed at the two end portions. As the method of erasing data of the NAND type memory cell, 0V is supplied to all control gates CG of the NAND column, and a high voltage (for example 20V) is supplied to selection gates SG1 and SG2 of the two selection transistors and the substrate Sub. Further, the source S and the bit line B are made open. By this, in the same way as the NOR type array, due to the Fowler Nordheim type tunneling phenomenon, electrons in the floating gate are drained, and the data of the entire NAND column is erased together.
However, in the semiconductor nonvolatile memory device of the related art, in the erase operation of data described above, it has been necessary to apply a high voltage as an operating voltage.
Further, along with the increase of the degree of integration and the enlargement of capacity of devices, a reduction of costs has been demanded. Particularly, lowering of costs is an indispensable condition in order to replace magnetic recording means.